hanbit h sd16m72d9a url:www.hbe.co.kr - 1 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) general description th e hsd16m72d9a is a 16 m x 72 bit synchronous dynamic ram high density memory module. the module consists of nine cmos 4 m x 8 bit with 4banks synchronous drams in tsop - ii 400mil package s on a 168 - pin glass - epoxy substrate. two 0 . 33 uf decoupling capacitors are mounted on the printed circuit board in parallel for each sdram. the hsd16m72d9a is a dimm(dual in line memory module) and is intended for mounting into 168 - pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applicatio ns a ll module components may be powered from a single 3.3 v dc power supply and all inputs and outputs are lv ttl - compatible. features ? p art identification hsd16m72d9a - f/10l : 1 00 mhz (cl= 3 ) hsd16m72d9a - f/10 : 1 00 mhz (cl= 2 ) hsd16m72d 9a - f/13 : 1 33 mhz (cl= 3 ) hsd16m72d9a - f/12 : 1 25 mhz (cl=3) f means auto & self refresh with low - power (3.3v) ? burst mode operation ? auto & self refresh capability ( 4096 cycles/64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs - latency (access from column address) - burst length (1, 2, 4, 8 & full page) - data scramble (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? the used device is 4m x 8bit x 4banks sdram synchronous dram module 128mbyte (8mx72bit),dimm with ecc based on 16mx8, 4banks, 4k ref., 3.3v part no . h sd16m72d9a
hanbit h sd16m72d9a url:www.hbe.co.kr - 2 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) pin assignment pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vss 29 dqm1 57 dq18 85 vss 113 dqm5 141 dq50 2 dq0 30 /cs0 58 dq19 86 dq32 114 nc 142 dq51 3 dq1 31 nc 59 vcc 87 dq33 115 /ras 143 vcc 4 dq2 32 vss 60 dq20 88 dq34 116 vss 144 dq52 5 dq3 33 a0 61 nc 89 dq35 117 a1 145 nc 6 vcc 34 a2 62 nc 90 vcc 118 a3 146 nc 7 dq4 35 a4 63 nc 91 dq36 119 a5 147 nc 8 dq5 36 a6 64 vss 92 dq37 120 a7 148 vss 9 dq6 37 a8 65 dq21 93 dq38 121 a9 149 dq53 10 dq7 38 a10 66 dq22 94 dq39 122 ba0 150 dq54 11 dq8 39 ba1 67 dq23 95 dq40 123 a11 151 dq55 12 vss 40 vcc 68 vss 96 vss 124 vcc 152 vss 13 dq9 41 vcc 69 dq24 97 dq41 125 clk1 153 dq56 14 dq10 42 clk0 70 dq25 98 dq42 126 nc 154 dq57 15 dq11 43 vss 71 dq26 99 dq43 127 vss 155 dq58 16 dq12 44 nc 72 dq27 100 dq44 128 cke0 156 dq59 17 dq13 45 /cs2 73 vcc 101 dq45 129 nc 157 vcc 18 vcc 46 dqm2 74 dq28 102 vcc 130 dqm6 158 dq60 19 dq14 47 dqm3 75 dq29 103 dq46 131 dqm7 159 dq61 20 dq15 48 nc 76 dq30 10 4 dq47 132 nc 160 dq62 21 cb0 49 vcc 77 dq31 105 cb4 133 vcc 161 dq63 22 cb1 50 nc 78 vss 106 cb5 134 nc 162 vss 23 vss 51 nc 79 clk2 107 vss 135 nc 163 clk3 24 nc 52 cb2 80 nc 108 nc 136 cb6 164 nc 25 nc 53 cb3 81 wp 109 nc 137 cb7 165 sa0 26 vcc 54 vss 82 sda 110 vcc 138 vss 166 sa1 27 /we 55 dq16 83 scl 111 /cas 139 dq48 167 sa2 28 dqm0 56 dq17 84 vcc 112 dqm4 140 dq49 168 vcc
hanbit h sd16m72d9a url:www.hbe.co.kr - 3 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) functional block dia gram cke clk cas dq0 - 7 ras dqm 0 c e w e a0 - a1 1 ba0 - 1 u1 /cas /cs0 /ras /cs2 cke0 dqm0 dqm 7 clkb clka cke clk cas dq 16 - 23 ras dqm 2 c e w e a0 - a1 1 ba0 - 1 c ke clk cas dq 32 - 39 ras dqm 4 c e w e a0 - a1 1 ba0 - 1 cke clk cas dq 48 - 55 ras dqm 6 c e w e a0 - a1 1 ba0 - 1 cke clk cas dq 8 - 15 ras dqm 1 c e w e a0 - a1 1 ba0 - 1 cke clk cas dq 24 - 31 ras dqm 3 c e w e a 0 - a1 1 ba0 - 1 cke clk cas dq 40 - 47 ras dqm 5 c e w e a0 - a 11 ba0 - 1 cke clk cas dq 56 - 63 ras dqm 7 c e w e a0 - a1 1 ba0 - 1 dqm2 dqm6 dqm4 dqm1 dqm3 dqm5 u 6 u 7 u 3 u 8 u 4 u 9 u 2 vcc vss two 0.1uf capacitor s pe r each s dram /we a0 - a11 ba0 - 1 dq0 - 63 cke clk cas cb0 - 7 ras dqm 7 c e w e a0 - a1 1 ba0 - 1 dqm1 cb0 - 7
hanbit h sd16m72d9a url:www.hbe.co.kr - 4 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) pin function descrip tion pin nam e input function clk system clock active on the positive going edge to sample all inputs. / c e chip e nable disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze operat ion from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+ tss prior to valid command. a0 ~ a1 1 address row/column addresses are multiplexed on the same pins. row address : ra0 ~ ra1 1 , column address : ca0 ~ ca 9 ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. / ras row address strobe latches ro w addresses on the positive going edge of the clk with ras low. enables row access & precharge. / cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. / we write enable enables write operation and row precharge. latches data in starting from cas, we active. dqm0 ~ 7 data input/output mask makes data output hi - z, tshz after the clock and masks the output. blocks data input when dqm active. (byte masking) dq0 ~ 63 data input/output dat a inputs/outputs are multiplexed on the same pins. vd d/ vss power supply/ground power and ground for the input buffers and the core logic. absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 1v to 4.6 v volta ge on vcc supply relative to vss vcc - 1v to 4.6 v power dissipation p d 9 w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 250 ma notes: permanent device damage may occur if " absolute maximum ratings" are exceeded. functional o peration should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
hanbit h sd16m72d9a url:www.hbe.co.kr - 5 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) dc operating con ditions ( recommended ope rating conditions (voltage referenced to vss = 0v, ta = 0 to 70 c) ) parameter symbol min typ . max unit note supply voltage vcc 3.0 3 . 3 3 . 6 v input high voltage v ih 2. 0 3.0 vcc+ 0.3 v 1 input low voltage v il - 0 . 3 0 0.8 v 2 out put high voltage v oh 2.4 - - v i oh = - 2ma out put low voltage v o l - - 0. 4 v i ol = 2ma input leakage current i l i - 1 0 - 1 0 ua 3 notes : 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = - 2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v dd q . input leakage currents include hi - z output leakage for all bi - directional buffers with tri - state outputs. capacitance ( v cc = 3.3v, ta = 23 c, f = 1mhz, vref =1.4v 200 mv) description symbol min max units clock c clk 2.5 4.0 pf / ras, / cas ,/we,/cs, cke, dqm c in 2.5 5.0 pf address c add 2.5 5.0 pf dq (dq0 ~ dq7) c out 4.0 6.5 pf d c characteristics (recommended operating condition unless otherwise noted, ta = 0 to 70 c) version parameter symbol test condition - 3 - 12 - 10 10l unit note operating current (one bank active) i cc1 burst length = 1 t rc 3 t r c (min) i o = 0ma 120 120 110 110 ma 1 i cc 2 p cke v i l (max) t cc =10ns 1 ma precharge standby current in power - down mode i cc 2 ps cke & clk v i l (max) t cc = 1 ma i cc 2 n cke 3 v i h (min) cs * 3 v i h (min), t cc =10ns input signals are changed one time during 20ns 20 precharge standby c urrent in non power - down mode i cc 2 ns cke 3 v i h (min) clk v i l (max), t cc = input signals are stable 7 ma i cc 3 p cke v i l (max), t cc =10ns 5 active standby current in power - down mode i cc 3 ps cke&clk v i l (max) t cc = 5 ma i cc 3 n cke 3 v i h (min), cs * 3 v i h (min), t cc =10ns input signals are changed one time during 20ns 30 active standby current in non power - down mode (one bank active) i cc 3 ns cke 3 vi h(min) clk vi l(max), t cc = input signals are stable 20 ma
hanbit h sd16m72d9a url:www.hbe.co.kr - 6 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 150 145 125 125 ma 1 refresh current i cc5 t rc 3 t r c (min) 220 220 210 210 ma 2 1.5 ma self refresh current i cc6 cke 0. 2v 800 ma notes: 1. measured with outputs open. 2. refresh period is 64ms. 3 . unless otherwise noticed, input swing level is cmos( v i h / v i l = v dd q / v ss q ). ac operating test conditions (vcc = 3.3v 0.3v, ta = 0 to 70 c) parameter value unit ac in put levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 operating ac parameter ( ac oper ating conditions unless otherwise noted) version parameter symbol - 13 - 12 - 10 - 10l unit note row active to row active delay t rr d (min) 15 16 20 20 ns 1 ras to cas delay t r p (min) 20 20 20 20 ns 1 row precharge time t r p (min) 20 20 20 20 ns 1 t ra s (min) 45 48 50 50 ns 1 row active time t ra s (max) 100 ns row cycle time tr c (min) 65 68 70 70 ns 1 last data in to row precharge t rd l (min) 2 clk 2 last data in to active delay t da l (min) 2 clk + 20 ns - + 3.3 v 1200 w 870 w 5 0 pf* d out v tt = 1.4 v 5 0 w 50pf d out z0=50 w v oh (dc) = 2.4v, i oh = - 2ma v ol (dc) = 0.4v, i ol = 2ma (fig. 1) dc output load circuit (fig. 2) ac output load circuit
hanbit h sd16m72d9a url:www.hbe.co.kr - 7 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) last data in to new col. address delay t cd l (mi n) 1 clk 2 last data in to burst stop t bd l (min) 1 clk 2 col. address to col. address delay t cc d (min) 1 clk 3 cas latency=3 2 number of valid output data cas latency=2 - 1 ea 4 notes : 1. the minimum number of clock cycles is determined by dividin g the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. .5. for - 8/h/l/10, trdl=1clk and tdal=1clk+20ns is also supported . ( recommend : trdl=2clk and tdal=2clk + 20ns. ) a c c haracteristics (ac operating conditions unless otherwise noted ) - 13 - 12 - 10 - 10l parameter symbol mi n max min max min max min max unit note cas latency=3 7.5 8 10 10 clk cycle time cas latency=2 t cc - 1000 - 1000 10 1000 12 1000 ns 1 cas latency=3 5.4 6 6 6 clk to valid output delay cas latency=2 t sac - - 6 7 ns 1,2 cas latency=3 2.7 3 3 3 output data hold time cas latency=2 t oh - - 3 3 ns 2 clk high pulse width t ch 2.5 3 3 3 ns 3 clk low pulse width t cl 2.5 3 3 3 ns 3 input setup time t ss 1.5 2 2 2 ns 3 input hold time t sh 0.8 1 1 1 ns 3 clk to output in low - z t slz 1 1 1 1 ns 3 cas latency=3 5.4 6 6 6 ns 2 clk to output in hi - z cas latency=2 t shz - - 6 7 ns notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2 - 0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered i e., [(tr + tf)/2 - 1]ns should be added to the parameter.
hanbit h sd16m72d9a url:www.hbe.co.kr - 8 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) simplified truth tab le command cke n - 1 cke n /c s /r a s /c a s /w e d q m ba 0,1 a10/ ap a11 a9~a0 note register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge disable h x l h l h x v h column address ( a0 ~ a 9) 4,5 auto precharge disable l column address ( a0 ~ a 9) 4 write & column address auto precharge disable h x l h l l x v h 4,5 burst stop h x l l h l x x 6 bank selection v l precharg e all banks h x l l h l x x h x h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down m ode exit l h l v v v x x dqm h x v x 7 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a12 & b a0 ~ b a1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. b a0 ~ b a1 : bank select addresses. if both b a0 and b a1 are "low" at read, write, row active and precharge, bank a is selected. if both b a0 is "low" and b a1 is "high" at read, write, row active and precharge, bank b is selected. if both b a0 is "high" and b a1 is "low" at read, write, row active and precharge, bank c is selected. if both b a0 and b a1 are "high" at read, write, row active and precharge, bank d is selected. if a1 0/ap is "high" at row precharge, b a0 and b a1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/wri te command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data - in a t the very clk (write dqm latency is 0), but makes hi - z state the data - out of 2 clk cycles after. (read dqm latency is 2)
hanbit h sd16m72d9a url:www.hbe.co.kr - 9 - hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) timing diagrams please refer to attached timing diagram chart (ii) p ackaging information unit : mm front view o r dering info rmation part number density org. package ref. vcc mode max.frq hmd16m72d9a - 13 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 133mhz hmd16m72d9a - 12 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 125mhz hmd16m72d9a - 10l 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 100mhz hmd16m72d9a - 10 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl2 100mhz hmd16m72d9a - f13 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 133mhz hmd16m72d9a - f12 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 125mhz hmd16m72d9a - f10l 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl3 100mhz hmd16m72d9a - f10 128byte 16m x 72 168 pin - dimm 4k 3.3v sdram cl2 100mhz f means auto & self refresh with low - power (3.3v)
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